reading

Cover
Title Page
Preface
1. P.1 The Dawn—Background of MM, MTM, and Mobility
2. P.2 Hardware for Mobility—The Focus
3. P.3 About this Book
4. Acknowledgment
5. References
About the Companion Website
1 MM and MTM for Mobility
1. 1.1 Convergence in Communications and the Future, 5G
2. 1.2 Review of Key Products in Communication Networks
3. 1.3 MM and MTM, an Intro to Hardware Technology
4. References
2 Interconnects
1. 2.1 Hierarchy of Interconnection
2. 2.2 Level 1, Interconnection Gap in FC‐PBGA, and Level 0.5
3. 2.3 Changing Dynamics of Semiconductor Manufacturing
4. References
3 State‐of‐the‐Art IC Packages, Modules, and Substrates
1. 3.1 Single‐Chip Packages (SCPs): Standardized Packages
2. 3.2 Advanced IC Substrates and Assembly
3. 3.3 Customized Assemblies: MCP/MCMs and Modules
4. References
4 Passives Technology
1. Not All the Passives are the Same: On‐Chip and Off‐Chip
2. Design Considerations Specific to Passives
3. 4.1 Thick‐Film Ceramic Technology (TFC) for MLC
4. 4.2 MLO Passives by Laminate Organic (LO)
5. 4.3 On‐Chip Passives
6. 4.4 Thin‐Film Multilayer (TFM) and IPD
7. 4.5 Summary on Passives Fabrication Technologies: Solutions for RF‐Passives Systems
8. References
5 Electrical Design for 5G Hardware—Digital Focus
1. 5.1 Introduction to PCB
2. 5.2 Signal Transmission Techniques: Singled‐Ended and Differential Signals
3. 5.3 Co‐Design Examples
4. 5.4 Wide I/O Memory Using TSVs
5. References
6 Electrical Design for 5G Hardware—RF Focus
1. 6.1 PHY, Modulated RF Carriers; a PoP Possible?
2. 6.2 Antennas
3. 6.3 RF Functional Components
4. 6.4 EMI/EMC
5. References
7 Product, Process Development, and Control
1. 7.1 Business Processes
2. 7.2 History of Statistical Approach for Quality Management
3. 7.3 APQP—An Iterative Process for Product and Process Development
4. 7.4 FMEA, Control Plan, and Initial Process Study
5. 7.5 PPAP and SPC
6. References
8 Product Life and Reliability Assessment
1. 8.1 Product Life Prediction
2. 8.2 Reliability Assessment
3. References
9 Hardware Solutions for 5G Mobility
1. 9.1 5G Mobility Products and Planar Solutions
2. 9.2 Advanced Interconnection and Future Business Model
3. 9.3 Finale—What’s Not
4. References
Appendices
1. A. Failure Mechanisms and Failure Analysis
2. A.1 Failure Mechanisms, or Macroscopic Models
3. A.2 Failure Analysis (FA) Techniques and FA Tools
4. References
B. ANOVA
1. B.1 One‐Way ANOVA
2. B.2 Two‐Way ANOVA
3. References
C. Gauge R&R and DOE
1. C.1 GR&R
2. C.1.1 AIAG’s Xbar/Range Method for Gauge R&R Study
3. C.1.2 Minitab
4. C.1.3 GR&R Casted in the ANOVA Format
5. C.1.4 Criteria
6. C.2 DOE
7. C.2.1 DOE Guidelines
8. C.2.2 2 Runs, Unreplicated Case
9. C.2.2.1 Concept of Blocking, 2 Run; Design Projection, a Hint of 2 · 2 Run
10. C.2.2.4 With a Center Point, k + 2 Run
11. C.2.3 Fractional Factorial Designs, 2 Run, p = 1, 2,.., < k
12. C.2.3.1 Aliasing, Confounding, and Resolution
13. C.2.3.2 Half FF Design, 2, or p = 1
14. Resolution
15. References
D. Statistics Tables
1. D.1 F Distribution
2. D.2 Poisson Table of Expected # of Occurrences at a Confidence Level (C.L.)
3. D.3 MR Percentile Table
4. References
Index
End User License Agreement

List of Tables

Chapter 01
1. Table 1.1 MM and MTM comparison.
2. Table 1.2 UE category for mobile modem.[56]
3. Table 1.3 Lithography techniques used for MPU/ASIC and DRAM and flash.[67] DP: dual patterning.
4. Table 1.4 Intel advanced transistor configurations at reducing feature sizes; *HKMG: high K metal gate.
5. Table 1.5 Transistor types for 22 nm technology node.[73]
6. Table 1.6 Gate length can be used adequately related to the progress in MM, until millennium.[75]
7. Table 1.7 Technology roadmap by ITRS.[76] Unit: nm.
8. Table 1.8 Flash memory volume production history, compared to the Intel roadmap, in bold. MLC: multi‐level cell, TLC: triple‐level cell.
9. Table 1.9 Volume production history for Intel products (x86 and Atom).
10. Table 1.10 Intel roadmap and volume production history for Apple’s A‐series SoCs (volume production by either TSMC or Samsung). Bold indicates the Intel roadmap.
Chapter 02
1. Table 2.1 Development of IBM’s Enterprise systems S/390 using MCM.[1]
2. Table 2.2 Pad metals used for wirebond and flip chip interconnections in Si and III‐V.
3. Table 2.3 Choices for low k or ultra low k materials and their properties.[16]
4. Table 2.4 Wirebonds and their bonding technique; TC: thermo‐compression.
5. Table 2.5 Intermetallics formed at the interface of wirebond and the pad metal, including those on chip (first bonding), MLO, MLC, or lead frame (second bonding).
Chapter 03
1. Table 3.1 A summary of advantages of the IC substrate and package.
2. Table 3.2 MLOs for IC substrates. Note the state of the art design rule for IC substrates is 8 µm/8 µm (line and spacing).
3. Table 3.3 High‐end performance FC‐PBGA applications.[34][35] DFR stands for dried film resist.
Chapter 04
1. Table 4.1 Fab technologies (baseline material sets and processing techniques) for the passives: on‐chip, EPs, and IPDs.
2. Table 4.2 Examples of dimensions and rated power for surface mount two‐terminal components[32] for imperial designation.
3. Table 4.3 MLOs for different HDI modules. SFC is from [34].
4. Table 4.4 HDI and standard features in mils.[38][39]
5. Table 4.5 Measured resistance of thin‐film titanium resistors.[78]
6. Table 4.6 Dielectric constant (ε_r) for selected dielectric materials.
7. Table 4.7 Capacitance density comparison.[82]
Chapter 05
1. Table 5.1 MLOs for PCBs.[3–5]
2. Table 5.2 Physical parameters of the single‐ended TSV.
3. Table 5.3 Extracted FC‐BGA and WB‐QFN package equivalent‐circuit elements.
4. Table 5.4 Co‐simulated and measured RF parameters of the LNA with and without the package effects.
5. Table 5.5 Performance comparison among LPDDR2, LPDDR3, and wide I/O; theoretical comparison (based on 0.5 fCV²) is from [42].
Chapter 06
1. Table 6.1 The worldwide ISM bands by ITU‐R (Article 5).
Chapter 07
1. Table 7.1 Software used in Chapters 7 and 8.
Chapter 08
1. Table 8.1 Regression results of Microsoft Excel excel4weibull‐calc.xls.[5]
2. Table 8.2 Activation energies for some failure mechanisms;[8] *TDDB: time‐dependent dielectric breakdown.
3. Table 8.3 Temperature cycling test conditions.
4. Table 8.4 General package reliability requirements for graphic DRAM devices.[16]
5. Table 8.5 β =2.164, η = 79.8 minutes for rivet CDF% from Table D3, and N = 5.
6. Table 8.6 Beta β = 2.024, η = 94.99 for rivet 2 using MR regression from adjusted ranks, see boltsmann‐adjranks‐calc.xlsx.
7. Table 8.7 Summary of rivet and rivet 2.
Chapter 09
1. Table 9.1 Mechanical properties of silicon and glass.[19]
2. Table 9.2 Underlying technologies for packaging forms needed to realize key 5G mobility products: (1) HD&L and (2) RF‐passives systems.
3. Table 9.3 Types of Cu to Cu bonding.
4. Table 9.4 Performance comparison among wide I/O, wide I/O 2, HBM, and HMC.
Appendix A
1. Table A.1 Failure modes, effects, and methods to identify root causes.
2. Table A.2 Marcoscopic root causes for IC level failure mechanisms; *time dependence dielectric breakdown.
3. Table A.3 Marcoscopic root causes for interconnect/PKG level failure mechanisms.
4. Table A.4 Microscopic tools to obtain images of samples. Resolutions from 1 µm, to 10 nm, 1 nm, and 0.1 nm and smaller; *e‐beam/x‐ray examples: AES (e‐beams, 5 to 10 nm, low > 50 eV), SEM/TEM (e‐beams, 0.4 and 0.9 nm, 30 KeV), and EPMA and EDS (x‐ray, 0.1 to 0.2 nm, 5 to 10 KeV).
Appendix B
1. Table B.1 Effectiveness data for three marketing strategies.[1]
2. Table B.2 One‐way ANOVA results: effectiveness of marketing strategies.
3. Table B.3 Two‐way ANOVA with repeated observations; *m is the # of repeated observations; note that the mean SS_error (MSE) is used in all F‐ratio calculation.
4. Table B.4 Credit card issued volume, by cities (First factor in row) and managers (second factor in column).[2]
5. Table B.5 ANOVA result on credit card issued volume.
6. Table B.6 Effectiveness of blood treatments (the only factor); adult, the human factor, has been ruled out.[1]
7. Table B.7 ANOVA result on effectiveness of blood treatments (the only factor).
Appendix C
1. Table C.1 AIAG data set for a gauge R&R study from [2].
2. Table C.2a Gauge R&R metric obtained using Xbar/range method from [2].
3. Table C.2b Gauge R&R metric obtained using Minitab using ANOVA method.
4. Table C.2c Calculation of gauge R&R study in ANOVA format, from grr‐excel‐anova‐calc‐DMAIC.xlsx.
5. Table C.3 Table for 2³ factorial design; treatment a is “+” for A and “–” for the rest.[3]
6. Table C.4 2⁶⁻² quarter fractional factorial (FF) design. The design generators (DGs) are E = ABC, F = BCD[3]).
7. Table C.5 Alias structure for 2⁶⁻², Resolution = IV.[3]
Appendix D
1. Table D.1 F_crit at significance level α = 0.05 [1].
2. Table D.2 Poisson table shows the expected number of occurrences for a specific occurrence n at a confidence level (C.L.) [2].
3. Table D.3 Median rank percentages for different number of specimens (integers) [3].

List of Illustrations

Preface
1. Figure P.1 IBM’s TCM used in mainframe computer System/370.
2. Figure P.2 Motorola’s BGA (OMPAC) illustration from US 5,239,198 A.[18]
3. Figure P.3 Key components in a modern handheld mobile. AP and mobile memory forms a PoP (packaged on a package).
4. Figure P.4 A guide to the chapters of the book.
5. Figure P.5 Convergence of communications: Internet and ISDN (POTS/PSTN), CS (circuit‐switched) and PS (packet‐switched), wireless WAN (2, G, 3G, and 4G) and wireless LAN (WLAN, sometimes abbreviated as wifi), and voice and data.
6. Figure P.6 RF‐passives systems include homogeneous RF CMOS and RF SoC and heterogeneous RF SiPs. Refer to Table 4.1 for passives technology.
7. Figure R.1 Computer architecture by John von Neumann.
Chapter 01
1. Figure 1.1 HKMG, three sides are high‐k dielectric, and the gate is metalized at the top surface.
2. Figure 1.2 A FinFET constructing from multiple TriGates; each ridge in a TriGate is covered on three sides.
3. Figure 1.3 A cross‐sectional view of AP(A4)/LPDDR combo in PoP for iPhone 4. Two rows of TMVs are conspicuous on each side.
4. Figure 1.4 In IMT 2000 development by 3GPP, GERAN (2.75G) and UTRAN (WCDMA) merged to form UMTS (3G).
5. Figure 1.5 B4G (Beyond 4G) and 5G.
6. Figure 1.6 Multi‐mode multi‐band, or MMMB.
7. Figure 1.7 A logic board of North American iPhone 5S.
8. Figure 1.8 IoT connection growth from 2010 to 2030.
9. Figure 1.9 Small cell solution for enterprise, public hotspot, and residential home.[14] Definitions of cells: macro‐cell: rural areas, highway; micro‐cell: a densely populated urban area; pico‐cell: a large office, a mall, or a train station; femto‐cell: home, or a small office.
10. Figure 1.10 5G key capabilities shown in solid line: User experienced data rate (0.1 to 1 Gbps), connection density (1 million users/km²), traffic volume density (tens of Tbps/km²), peak data rate (tens of Gbps), and end to end latency in ~1 ms;[10] for comparison, 4G capabilities are shown using the dashed line.
11. Figure 1.11 Data capacity improvement through denser cells.
12. Figure 1.12 Node B in 3G UTRAN.
13. Figure 1.13 Beamformer focuses on a small cell (sector).[18]
14. Figure 1.14 Massive‐element antenna (right) is able to focus on individual UEs.[18]
15. Figure 1.15 Extended copper to 10 Gbps and hand off to optical fiber thereafter. Cloud computing uses Ethernet 802.3 employing GbE [19].
16. Figure 1.16 Cross section of twisted pairs and RJ45 connector for data (Cat 6), left and middle; a proprietary connector, right.
17. Figure 1.17 A core technology for GbE, the quad small form‐factor pluggable (QSFP), serializer and de‐serializer (Serdes) operations, photo‐diode (PD) converts optical signals to electrical ones.[31]
18. Figure 1.18 A QSFP module, the upper figure; and the laser transmitter module.[34,35]
19. Figure 1.19 An Intel chipset, which is implemented on a motherboard (SoB),[37] which consists of a CPU (with the heat sink removed), north bridge, and south bridge.
20. Figure 1.20 A desktop computer (x86 based) connects to GbE using PCIe; MCH is the north bridge, ICH2 is the south bridge shown in Figure 1.19.
21. Figure 1.21 A GPU card, where a huge heat sink is attated to the GPU die.
22. Figure 1.22 Routers provide connection between CS (landline for voices) and PS (WWW for data).
23. Figure 1.23 ARM architecture: ARM core processor, buses, and the peripheral I/Os on an ARM single chip.
24. Figure 1.24 2G/3G modem and the front end (transceiver, switches, filters, and PAs).[9][54]
25. Figure 1.25 MSM, left, and RF FE, right, consisting of a transceiver/UE category 3 modem and RF circuits.
26. Figure 1.26 Antennas at a base‐station (a), left and antennas of an indoor wifi router (b), right.
27. Figure 1.27 iPhone 4S primary, secondary, and wifi/bluetooth antennas.
28. Figure 1.28 A wifi transceiver next to MAC/BB.
29. Figure 1.29 Li‐ion battery (bound by the white border, 1‐3/4” by 2‐1/2”) in a smartphone (2‐1/4” by 4”) with 1,300 mAh, 4.81 Whr capacity.
30. Figure 1.30 Moore’s law: the transistor counts double every two years.
31. Figure 1.31 TriGate configurations by Intel; the ridges hugged by the gate are drain‐source: (into the paper).[73]
32. Figure 1.32 A planar bulk Si MOSFET[74] and definition of pitch (S‐D) and gate length.
33. Figure 1.33 Metal 1 pitch (source drain) and half pitch definitions, the figure is obtained from Figure 1.32 by the viewing angle.[75]
34. Figure 1.34 A 3D FinFET, and definition of fin pitch, fin width, pitch (G‐G), and channel length.
35. Figure 1.35 Technology nodes: 22 nm (2011) and 14 nm (2013).
36. Figure 1.36 Trend of NAND flash memory (most aggressive silicon technology); design rule (DR) versus year.
37. Figure 1.37 The process technology employed for x86 and Atom within Intel.
38. Figure 1.38 A7 (left) and A8 (right), where CPU and GPU cores along with PLLs are shown.
39. Figure 1.39 Combined x86 and A‐series ARM SoC products by Intel and Apple, respectively.
40. Figure 1.40 The left‐most figure shows Intel Core^TM2 quad processor (Q8300) with metal lid sitting on the socket shown in the middle (a LGA 775 with a bed of spring connectors, see Figure 3.10 in Chapter 3); the right figure shows the bottom LGA pads of the processor. Note that the spring connectors and the round LGAs are one‐to‐one in match.
41. Figure 1.41 A de‐processed application processor for A6.
42. Figure 1.42 A ball grid array (BGA) external views: top (left), bottom (right).
43. Figure 1.43 Power consumption for x86 CPU in the chipset and Atom (SoC).
44. Figure 1.44 Radar chart for a CPU in a chipset and a single chip (SoC).
45. Figure 1.45 Broadcom’s bare die, BCM5976, is next to TI’s SoC shown in Figure 1.7.
46. Figure 1.46 Kinston’s memory module made from BGA packaged memory ICs.
47. Figure 1.47 Early and concept drawing of packaged on a package (PoP) packaging form.
48. Figure 1.48 A bare die BCM4334 on Murata’s wifi RF module 339S0205.[90]
49. Figure 1.49 A bare IC, BCM4334.
50. Figure 1.50 MTM‐PKG map: X‐axis being the level of integration (from amorphous to 2D, to ≥2D), y‐axis being the degree of monolithicity (from hybrids to monolithic‐based).
51. Figure 1.51 Classification of MM and MTM; two different business models; one with high margins (MM), the other with less margins (MTM).
52. Figure P.7 Computer architecture by John von Neumann.
Chapter 02
1. Figure 2.1 Illustration of XY and Z interconnections, see also Figure P.2.
2. Figure 2.2 IBM’s C4 on LTCC.[1]
3. Figure 2.3 Illustration of a gap in interconnection: traces in Cu/low‐k BEOL and those on IC substrate are drastically varied in size.
4. Figure 2.4 U.S. Patent 3,138,743 for “miniaturized electronic circuits,” the first integrated circuit, was filed on February 6, 1959.
5. Figure 2.5 Delay time for heavily doped polysilicon, WSi₂, W, and Al for minimum feature sizes of 5, 1, and 0.5 µm.[4]
6. Figure 2.6 Global, semi‐global (intermediate), and local (lower layers) distributions in Cu/low‐k BEOL (back end of the line). The bottom is close to the active logic gate area, the top is to be wirebonded or flip chip bumped (Level 1 interconnection).[5][6][7]
7. Figure 2.7 A cross section of a transistor and its interconnection.[12]
8. Figure 2.8 Aluminum pads for wirebond (low # I/Os) and flip chip interconnections (low and high # I/Os); low‐k FC may not need re‐distribution.
9. Figure 2.9 Wirebonds on Al pads.
10. Figure 2.10 UBM and Cu/low‐k, RDL for a flip chip bumped silicon IC.
11. Figure 2.11 Additive Damascene techniques (for Cu, left) and conventional subtractive etching (for Al, right). [5] [6] [15]
12. Figure 2.12 Dual Damascene.[5][6][15]
13. Figure 2.13 GaAs Au backside via (BSV) hole processing steps.[25] After the GaAs etching, the BSV is formed by first Ti/Au seed metallization, followed by Au electroplating.
14. Figure 2.14 Wirebonds as a Level 1 interconnection in a QFN (X‐ray).[28] Dashed line at the bottom figure indicates the active side of the IC. See Figure 3.2 in Chapter 3for terminology.
15. Figure 2.15 (a) Rent’s rule, correlates number of logic gates to the number of I/Os; (b) number of I/O pads can be accommodated by peripheral and areal types of interconnection.
16. Figure 2.16 WB‐PBGA (left) and FC‐PBGA (right), where ball grid array (BGA) balls are used as Level 2 interconnection; dashed lines indicate the active sides of the ICs.
17. Figure 2.17 Wirebonds in a LTCC package; dashed line depicts the active side of the ICs.
18. Figure 2.18 Ball‐wedge wirebonding (left, the ball bonding being the first) and wedge‐wedge (right).[33]
19. Figure 2.19 Forming gas is required during the Cu free air ball (FAB) formation.[35]
20. Figure 2.20 Bond wire looping and the wirebond profiles.[32]
21. Figure 2.21 Spikes occur at the Al‐Si interface.
22. Figure 2.22 Different UBMs[45] and processing techniques for Al pads.
23. Figure 2.23 Bumping methods.
24. Figure 2.24 UBM and bumping choices for Cu/low‐k with RDL top layers.
25. Figure 2.25 TSV and micro‐bumps, 2.5D silicon interposer; TSV and micro‐bumps are considered as Level 0.5.
26. Figure 2.26 TSV processing steps for 2.5D silicon interposer.
27. Figure 2.27 TSVs and microbumps used in 3D IC MCPs; active interposer: face to face (F2F, left), face to back (F2B, right); bold lines indicate the orientation of the active side.
28. Figure 2.28 Via middle, TSVs are done in a wafer fab foundry.
29. Figure 2.29 Via last, FEOL, BEOL followed by thinning (MEOL) and TSV processes (via etching and filling).
30. Figure 2.30 Processing steps for forming blind TSVs.
31. Figure 2.31 Void‐free copper filling.[55]
32. Figure 2.32 The CMP grinding process.[55]
33. Figure 2.33 Via reveal processing steps.
34. Figure 2.34 2.5D silicon interposer after bumping process (microbumps and flip chip bumps): F2F (left), F2B (right).
35. Figure 2.35 After bumping process (microbumps and flip chip bumps): F2F (left), F2B (right), corresponding to 3D IC configurations shown in Figure 2.27.
36. Figure 2.36 Vertical (left) and horizontal (right, from top) views of a TSV interconnect.[64]
37. Figure 2.37 Shinko’s 2.5D silicon interposer.[66]
38. Figure 2.38 2.5D silicon interposer by ITRI;[67] Level 0.5 TSVs are used.
39. Figure 2.39 AIST and TUS micro Au bumps: line width 20 µm, spacing 15 µm, bump height 2 µm.[71]
40. Figure 2.40 Concept drawing of opper pillar bumps with tin‐Cu solder on the top, from [72].
41. Figure 2.41 Division of front and back ends in the old days, CMOS: devices making, Passiva: passivation, Open: passivation opening, WB: wirebonding; front end and back end may be closedly collocated under one roof.
42. Figure 2.42 Back end includes UBM and bumping; UBM/B: UBM and bumping; front end and back end may occur in a half globe away.
43. Figure 2.43 Bumping is a new added business manufacturing landscaping. Bumping can be a separated entity, or part of an OSAT.
44. Figure 2.44 Front‐end processes include FEOL and BEOL (Cu/low‐k); the traditional wafer foundries (WFs) may add a section called wafer‐level planar (WLP) to address the needs for BEOL and MEOL. Again, back end may be a half‐globe away.
45. Figure 2.45 Ideal 2.5D silicon interposer manufacturing; TSV: TSV formation, Rde‐dis: re‐distribution layers, Thinn: thinning, Reveal: via revealing.
46. Figure 2.46 3D IC Via middle (VM) model.
47. Figure 2.47 3D IC Via last (VL) approaches; TSVs are etched through thinned silicon in the first approach (top); TSVs are etched from the BEOL side in the second approach (bottom).
Chapter 03
1. Figure 3.1 WTR1625L RF Transceiver in WL‐CSP, W stands for wafer level, L stands for LTE.
2. Figure 3.2 Final form of a lead frame single‐chip package.
3. Figure 3.3 TAB (tape automated bonding); the inner lead bonds (ILBs) connect the chip, the outer lead bonds (OLBs) connect to the next level (e.g., the substrate).
4. Figure 3.4 CSP (using a rigid or a flex, left) and WL (wafer level)‐CSP (the organic interposer is a PI or BCB dielectric as a re‐distribution layer, two on the right, not to scale).
5. Figure 3.5 Sub‐die metal patterns on a PBGA and RDL layer on a CSP.
6. Figure 3.6 eWLB‐WLP to produce WL‐CSP (FI) or eWLB (embedded wafer level BGA).
7. Figure 3.7 eWLB from STMicroelectronics,[13] Stats ChipPAC, and Infineon; WL‐CSP is fan‐in (FI), whereas eWLB is fan‐out (FO).
8. Figure 3.8 Organic interposer based BGA has many related packaging forms; SCP (single‐chip package) and MCM/MCP for digital mobile and high‐performance computing; modules/SiPs (in the gray area) for mobile‐wireless computing. SCPs are monolithic and standard products, whereas MCM/MCP and modules are hybrid, consisting of many passives, and in customed forms.
9. Figure 3.9 A pin grid array (PGA) and its socket: A detailed cross‐section view of PGA (top); the PGA and its socket.
10. Figure 3.10 Land grid array (LGA) and the socket; bed of spring interconnects are on the top of the socket.
11. Figure 3.11 Die‐above and die‐under configurations for CPU inside the IHS or copper slug heat spreader. BT laminate, wirebond connecting CPU to OLGA (organic LGA). Pins can be replaced by lands. In both configurations, die faces downward.[24] Pin‐ or land‐grid array (PGA or LGA) single‐chip packages are illustrated in Figures 3.9 and 3.10.
12. Figure 3.12 A chip on board (CoB) or wirebond direct chip attach (DCA), left; and FC DCA, at right. For reliability reasons, UF (underfill) may be applied.
13. Figure 3.13 IC packaging processes for lead framed single‐chip packages: QFN, WB‐PBGA, and FC‐PBGA.
14. Figure 3.14 Capillary action in dispensing underfill.
15. Figure 3.15 IC packages that employ organic interposer (OI): wirebond (WB, top), flip chip (FC, bottom).
16. Figure 3.16 Back‐end processes: Packaging and testing for single‐chip packages. WAT: wafer acceptance test, CP: circuit probe, BI: burn‐in, FT: final test.
17. Figure 3.17 MTM‐substrate map: Y‐axis being the substrate types
18. Figure 3.18 Fabrication and assembly for a FC‐PBGA; assembly includes flip chip bumping, solder masking, fluxing, reflow, underfill, and BGA attach.
19. Figure 3.19 Thickness of an FC‐PBGA is determined by the core thickness and the number of BU layers.[40]
20. Figure 3.20 Semi‐additive metallization process (SAP) for ABF used as a build‐up layer.
21. Figure 3.21 Conceptual drawings of GE’s HDI chip‐on‐flex multichip/single‐chip process flow “chip first” overlay technology.[43]
22. Figure 3.22 2D Multichip module.[45]
23. Figure 3.23 A 3D stacked packaging technology for MCP (multi‐chip package) by Toshiba.
24. Figure 3.24 Fully molded PoP base package with a FC die, SMT passives with TMV technology connecting to standard combo memory type top package. Refer to Figure 1.3 (tear‐down) and Figure 1.47 (PoP is a combo of two BGAs).
25. Figure 3.25 The bottom can be fabricated using FO (eWLB), followed by TMV or TEV steps.[49]
26. Figure 3.26 TEV and TSV to implement PoP.
Chapter 04
1. Figure 4.1 Circuits produced by using silicon monolithic/FEOL and BEOL technologies.
2. Figure 4.2 MTM map (passives technology): y‐axis being the technology types. Passive technologies: FEOL and BEOL, TFC (thick‐film ceramic), LO (laminate organic), and TFM (thin‐film multilayer) are discussed in this chapter.
3. Figure 4.3 Power supply system with a wrongly placed decoupling capacitor C.
4. Figure 4.4 Edge and shape of LTCC thick‐film; a elliptical cross section, with cross‐sectional area A (~1.8 mils²), minor radius B (~0.2 mils) and major radius C (~2.25 mils).[8]
5. Figure 4.5 Filler metal and workpieces in brazing process for pin grid array (PGA).
6. Figure 4.6 LTCC manufacturing processes.[20]
7. Figure 4.7 Aligned through vias after co‐firing.
8. Figure 4.8 Top and buried LTCC (post‐ or co‐fired) resistors and their method of trimming; high voltage pulses delete or activate transitions in the microstructure of the resistor, and change the resistor value.[21]
9. Figure 4.9 LTCC multi‐layer capacitor (a),[24] and dielectric tapes of different Dks (b).[25]
10. Figure 4.10 LTCC 2‐turn inductor, Qs were in the 40 to 50 range;[26] L/S = 8/8 mil.
11. Figure 4.11 AiP cross‐sectional view; slot radiator is featured on the second layer, the antenna ground on the fourth layer, package ground is on the first layer (radiator and its group are shown as dashed line). Silver was the metallization for the MLC, gold wirebonds were used to connect signals and ground from the Tx Rx ICs to the ceramic package.
12. Figure 4.12 Core and pre‐preg layers of an MLO; B‐stage is the resin partially cured, C‐stage is those fully cured.
13. Figure 4.13 RCC made of Cu (top) and resin 12 or 18 µm of Cu, resin 60 or 80 µm.
14. Figure 4.14 Capture pads, aligned at the left, and not aligned at the right.
15. Figure 4.15 Cross‐section view of the embedded passives.
16. Figure 4.16 Geometrical configuration of the organic bandpass filter designed for 2.45 GHz WLAN applications.[41]
17. Figure 4.17 A RF module that integrates RFIC, base‐band, and RF passives.
18. Figure 4.18 Reflow of discrete components and a KGB die FC to a module’s substrate.[45]
19. Figure 4.19 MEMS and antenna are integrated using the EP heterogamous integration technology.
20. Figure 4.20 Layout of Tx package with highlighted high‐speed interconnects, antennas, and pads for balls and chip joints.[47]
21. Figure 4.21 Cross‐sectional view of solder mask defined (SMD, left drawing) and non‐solder mask defined (NSMD, right drawing) pads.
22. Figure 4.22 Contact angle at the surface between molten liquid and the solid.
23. Figure 4.23 RF isolation technique using guard ring technique. Erisson‐STMicroelectronics.[50]
24. Figure 4.24 RF isolation technique using polysilicon patterned ground shield (PGS) technique. On top layer lay there are Al inductors, SiO₂ is between the Al and silicon substrate (left); polysilicon PSG is added beneath SiO₂.
25. Figure 4.25 Polysilicon patterned ground shield (PGS).[51]
26. Figure 4.26 On‐chip resistors from FEOL; concept drawings from [58].
27. Figure 4.27 On‐chip capacitors in FEOL; concept drawings from [58].
28. Figure 4.28 On‐chip passives in BEOL,[60], see Figure 4.1 completed with FEOL.
29. Figure 4.29 On‐chip interconnections need barrier layers to enhance the integirty and performance of the interconnection.
30. Figure 4.30 Sputtering chamber.
31. Figure 4.31 Electrolytic plating of a metal with copper in a copper sulfate bath.
32. Figure 4.32 Lift‐off process: (a) substrate, (b) sacrificial layer (e.g., a photoresist), (c) patterning the sacrificial layer, (d) deposition (through sputtering) of target layer (e.g., a metal), (e) removing the sacrificial layer (through solvent), and (d) the final result.
33. Figure 4.33 On the left, general principles of negative (l) and positive (r) photoresists.[3]
34. Figure 4.34 Silicon interposer using thin‐film and organic processes;[77] dual‐step ABF laminates were used to construct multilayer.
35. Figure 4.35 A cross section view of silicon interposer with passive circuits (R, L, and C).[78]
36. Figure 4.36 Thin‐film resistor.[78]
37. Figure 4.37 Thin‐fim inductors.[78]
38. Figure 4.38 Measured inductance for 200 µm‐square, 400 µm‐square, and 800 µm‐square inductors.
39. Figure 4.39 Fabrication process step of the thin‐film capacitor, Ta₂O₅.[78]
40. Figure 4.40 Capacitance versus frequency for the thin‐film capacitors.
41. Figure 4.41 Silicon (hi‐resistivity) thin‐film embedded passives technology.[79]
42. Figure 4.42 Glass TF IPD from NCU.[81]
43. Figure 4.43 FIZM’s WL‐IPD multi‐layer over a substrate (silicon, alumina, or glass).[87]
44. Figure 4.44 Different wafer level‐IPDs[87]; 1. and 2. are chip‐like IPDs; 3. through 6. are considered as module‐like IPD‐SiPs (IPDs act as carriers, and having taken one more integration into 3D structures); discussion of chip‐like IPD and module‐like IPD‐SiPs will be given later, Section 4.4.2.4.
45. Figure 4.45 Silicon IPD processing from StatsChipPAC.[83]
46. Figure 4.46 Glass IPD processing from STMicroelectronics.[83]
47. Figure 4.47 A glass IPD on top of a laminate, from STMicroelectronics.[83]
48. Figure 4.48 Originally, IPD was employed for impedance matching on top of GaAs. It it also being treated as an SMT, and taking these configurations.
49. Figure 4.49 Conceptual drawings of applications of IPDs: IC and IPD in a WB‐PBGA (left) and IPD is integrated in the eWLB process (right).
50. Figure 4.50 A LNA is attached to a glass‐IPD.[81]
51. Figure 4.51 IPD carries a PA and uses wirebond interconnection (left BGA‐1 and QFN), or the nested configuration uses flip chip interconnection (right BGA‐2).
Chapter 05
1. Figure 5.1 HD&L and RF FE are two key blocks in a smartphone. HD&L includes AP and its mobile memory; RF FE consists of a transceiver, PA/SW modules, an antenna tuning module, and antennas.
2. Figure 5.2 Key devices in Apple’s iPhone 6.
3. Figure 5.3 Current devices and components that are SMT to PCB for smartphone: carries packaged IC, modules, discrete components, DCA, connectors, lids for shielding.
4. Figure 5.4 State‐of‐the art electronic components on a PCB.
5. Figure 5.5 Single‐ended (SE, left) and differential (DF, right) signaling techniques.
6. Figure 5.6 Single‐ended (S‐G) and differential (S⁺S⁻G) Signals. In differential signals, the ground can be the virtual or a physical one.
7. Figure 5.7 Symmetrical coupled transmission lines.[9]
8. Figure 5.8 Asymmetrical coupled transmission lines, the substrate is epoxy glass with ϵ_r = 4.7.[8]
9. Figure 5.9 Schematic of a coupled line probed singled endedly.
10. Figure 5.10 Coupled transmission lines are driven differently, odd mode (left) and even mode (right). Different impedance Z_0,o, Z_0,e, Z_diff, and Z_comm are illustrated. Vias bring the ground to the signal plane, so single ended probing can be performed (Figure 5.11).
11. Figure 5.11 Schematic of a coupled line probed using mixed mode signals.
12. Figure 5.12 Single‐ended transmission line (left) and differential pair passing a ground with a slot. On the right, the virtual ground is represented by the dashed line.
13. Figure 5.13 Differential signals are used to drive the two‐line transmission line.[19]
14. Figure 5.14 Resultant signal received after obtaining V_diff.[19]
15. Figure 5.15 In a typical measurement system, the instrument and circuit under test may have separate grounds.
16. Figure 5.16 A two‐line transmission line driven by a differential signal; the line lengths are different.[19]
17. Figure 5.17 Signals at the receiving end; equal length at left; un‐equal lengths at right.[19]
18. Figure 5.18 (a) Microstrip line and a differential pair as the victims to a microstrip aggressor; (b) a twisted pair as a victim to a microstrip aggressor.[23]
19. Figure 5.19 Eye diagrams.[25]
20. Figure 5.20 Physical modeling of a single‐ended TSV in GSG configuration.
21. Figure 5.21 A three‐wire transmission line.
22. Figure 5.22 A double‐sided probe station for TSVs (or other TSV‐like structures) characterization, RF and Microwave Lab, NSYSU.
23. Figure 5.23 A schematic and a chip photo of the LNA in a CMOS WLAN receiver.
24. Figure 5.24 3‐D structure of the LNA and its package pin assignment in (a) the FC‐BGA packaged WLAN receiver IC and (b) the WB‐QFN packaged WLAN receiver IC.
25. Figure 5.25 Two‐port equivalent circuit for representing the input/output chip‐package interconnect effects on the LNA.
26. Figure 5.26 (a) 3‐D structure and package pin assignment for the FC‐BGA packaged line die serving as a modeling kit. (b) Equivalent circuit for the packaged line die.
27. Figure 5.27 (a) 3‐D structure and package pin assignment for the FC‐BGA packaged short‐circuited die serving as a modeling kit. (b) Equivalent circuit for the FC‐BGA packaged short‐circuited die.
28. Figure 5.28 Comparison between modeled and measured results of (a) S₁₁ on the Smith chart and (b) normalized magnitude of S₂₁ in decibels for the packaged line die.
29. Figure 5.29 (a) 3‐D structure and package pin assignment for the FC‐BGA packaged CMOS spiral inductor. (b) CMOS spiral inductor model considering the flip‐chip ground‐proximity effect.
30. Figure 5.30 Modeled and measured S‐parameters for the 6.5‐turn CMOS spiral inductor. (a) Without FC‐BGA package. (b) With FC‐BGA package.
31. Figure 5.31 Magnitudes of S₂₁ parameter of the LNA with and without the package effects: (a) co‐simulated results and (b) measured results.
32. Figure 5.32 Measured and simulated S11 and S21.[38]
33. Figure 5.33 Measured and simulated S11 and S21.[39]
34. Figure 5.34 A x86 memory for enterprise systems.
35. Figure 5.35 Mobile AP and its main memory architecture.
36. Figure 5.36 Mobile memory from JEDEC website.[40]
37. Figure 5.37 Memory DDR3 in enterprise systems.
38. Figure 5.38 Direct contact between the upper and lower probes as a thru kit.
39. Figure 5.39 Comparison of the S‐parameter results among equivalent circuit, HFSS simulation, and measurement for the TSV in GSG configuration. (a) | S₂₁ | (b) ∠S₂₁ (c) | S₁₁ | (b) ∠S₁₁
40. Figure 5.40 Demonstration of wide I/O (Gen 1) mobile memory, four channel, 16‐bank configuration.[40]
Chapter 06
1. Figure 6.1 Frequency‐dependent attenuation of electromagnetic waves in standard atmosphere.
2. Figure 6.2 A digital pulse train.[1]
3. Figure 6.3 Two popular structures: transmission line (left) and a monopole antenna‐feed system (right).
4. Figure 6.4 Image and ground return currents for a microstrip transmission line (left); image and ground return currents for a monopole antenna (right).
5. Figure 6.5 Differential feed for half wavelength dipole antenna.
6. Figure 6.6 Differential feed for a loop antenna; 2π · r (radius) = half wavelength.
7. Figure 6.7 Folded dipole is a compress loop antenna, but, it behaves like a dipole from the above illustration.
8. Figure 6.8 Yagi‐Uda antennas: one left, a free space antenna, where the reflector is 5% longer, and the directors are 5% shorter than the dipole; on the right, a Yagi‐Uda antenna on silicon is shown.
9. Figure 6.9 Single‐ended feed for quarter wavelength monopole antenna is derived from a dipole (the left), treating the other element as the ground (like it in the middle figure). The right is a planar monopole.
10. Figure 6.10 Inverted L antenna and printed inverted‐F antenna (PIFA).
11. Figure 6.11 Two PIFA‐like MIMO antennas stationary S/S are indicated by two Xs in the right figure.[7]
12. Figure 6.12 Microstrip‐patch (left) and a PIFA (right, “P” in PIFA for planar) antenna.[8]
13. Figure 6.13 Radiation pattern for a patch; the useful E‐fields are out of the plane.
14. Figure 6.14 An array is a sampled aperture antenna. In the excitation space, the sampling rate is d/λ.
15. Figure 6.15 Antenna mode current (AMC). In a single endedly fed system, because of asymmetrical feed structure, there is unbalanced current occurring (I₂) on the surface of the ground of the feed system, while balanced I₁ and –I₁ are flowing inside the feed.
16. Figure 6.16 P_in (input power), P_ant (power delivered to antenna), and P_rad (radiated power) for an antenna efficiency measurement system.
17. Figure 6.17 Planar (patch) dual‐port antenna by [26] reports efficiency of 80% to 90% from 2.5 GHz to 2.7 GHz.
18. Figure 6.18 Conventional Marchand balun.[37]
19. Figure 6.19 At 1.0 GHz center frequency; 0.6 and 1.4 GHz are far from 1.0 GHz.[37]
20. Figure 6.20 Cross‐sectional view of an IPD on a glass substrate.
21. Figure 6.21 Block diagram of a balun‐integrated bandpass filter.
22. Figure 6.22 Transformer‐coupled bandpass filter design: (a) top view layout and (b) top view photograph.
23. Figure 6.23 Comparison of the magnitude of S₂₁ and S₁₁ between EM simulation and measurement for the transformer‐coupled bandpass filter.
24. Figure 6.24 Comparison of the group delay between EM simulation and measurement for the transformer‐coupled bandpass filter.
25. Figure 6.25 Balun‐integrated bandpass filter design: (a) top view layout and (b) top view photograph.
26. Figure 6.26 Comparison of the magnitude of S_D1 and S₁₁ between EM simulation and measurement for the balun‐integrated bandpass filter.
27. Figure 6.27 Comparison of the CMRR and group delay between EM simulation and measurement for the balun‐integrated bandpass filter.
28. Figure 6.28 Switch (left), duplexer (middle), and diplexer (right).
29. Figure 6.29 Sources of EM interference.
30. Figure 6.30 Complex‐valued near‐field scanning system.
31. Figure 6.31 Two on‐PCB differential lines without and with bend discontinuities.
32. Figure 6.32 Magnitude and phase color map plots with respect to the near‐field component H_y in the differential lines without bend discontinuities.
33. Figure 6.33 Magnitude and phase color map plots with respect to the near‐field component H_y in the differential lines with bend discontinuities.
34. Figure 6.34 Decoupling capacitor[40] is used to complete the ground return path.
Chapter 07
1. Figure 7.1 Strategic management in charge of core competence.
2. Figure 7.2 Process development cycle, which employs FMEA to reduce potential risks, establish pre‐launch pre‐control plan, and conduct IPS.
3. Figure 7.3 An FMEA worksheet; after each failure mode, effects (severity), causes (occurrence), and control (detection) are evaluated. RPN (= severity × occurrence × detection) for each failure mode is calculated.
4. Figure 7.4 Cause and effect brainstorm in a fishbone diagram (Ishikawa technique).
5. Figure 7.5 A trend was identified in the X‐bar and R control chart.
6. Figure 7.6 When the process is centered ( and the target value match), C_p is obtained.
7. Figure 7.7 The center of the process is biased toward the USL, C_pk is obtained.
Chapter 08
1. Figure 8.1 A high shape factor (β > 1) Weibull may be used to predict the first failure (i.e., the product life).
2. Figure 8.2 Bathtub curve, including Weibulls of different βs. time is normalized to the scale factor η; β (beta)is the shape factor.
3. Figure 8.3 A Weibull plot where the parameters shape and scale factors are obtained.
4. Figure 8.4 Dynamic stress by input stimulus for toggling the internal nodes of the device.
5. Figure 8.5 (a) (top) and 5(b) (bottom). Coding censored specimens.
6. Figure 8.6 Without and with censored data in minutes; rivet and rivet 2, respectively.
7. Figure 8.7 Rivet data processed using Minitab (MLE).
8. Figure 8.8 Rivet 2 data using Minitab (MLE).
Chapter 09
1. Figure 9.1 FPGA slices are fabricated and then integrated using a silicon interposer.
2. Figure 9.2 PoP packaging solutions (not to scale) for mobile high‐density and logic products: early PoP (left), FO‐PoP (middle), and (InFO‐PoP by TSMC,[4] right).
3. Figure 9.3 InFO‐WLP from TSMC.[25] [26]
4. Figure 9.4 FO/InFo WLP (the left one, all TFM, 2.0+D) has a whole TFM; cost‐effective versions (the right two) employ TFM+package substrate (2.1D).
5. Figure 9.5 Dual‐die in 2D formats: All‐TFM‐RDL (2.0+D, left), TFM‐RDL+Organic substrate (2.1D, middle), and 2.5D SI (right) packaging solutions (all not to scale) for mobile high‐density and logic products.
6. Figure 9.6 Two 2.5D‐SI alternative approaches: 2.0+D FO/InFO (on the left) from Infiineon and TSMC and 2.1D TSV‐less (NTI, or SLIT from SPIL[6] (on the right).
7. Figure 9.7 3D IC Packaging solutions (not to scale) for high‐density and logic AFC MCP: TSV‐based (left) and Cu‐to‐Cu pad bonding based (right).
8. Figure 9.8 C2W wafer level planar processes: (1) alignment, (2) and (3) securing the die on top of the wafer, spin coat a layer of polymer (4) for further securing the die,[29] [30] and lastly, grinding (4).
9. Figure 9.9 RF MoM (module on a module) is illustrated, similar to Qualcomm’s RF PoP (packaged on a package) for RF360^TM.[31]
10. Figure 9.10 (a) (MoM‐1) and (b) (MoM‐2) for realizing critical RF and modem circuits.
11. Figure 9.11 Concept drawing of SiP Module by ASE; key characteristics: disctete passives (e.g., 0402, 0201, 01005 using MLC) and organic (HDI modules using MLO).
12. Figure 9.12 Concept drawing of IPAC (integrated passive and active components), a heterogeneous platform technology for RF‐passives systems by Ga Tech.[11]
13. Figure 9.13 More examples of IPAC.
14. Figure 9.14 Adding an antenna turns an active bearing IPD (such as Figure 4.50, Chapter 4) into an antenna‐IPD (also an IPD‐SiP).
15. Figure 9.15 An example of A‐IPD.
16. Figure 9.16 A 2.5D glass interposer (GI), which carries three die, sits on a ceramic multilay (MLC).[18] The three die consititute an RF‐passives integrated system.
17. Figure 9.17 Future electronic components on a PCB, as compared to Figure 5.4 in Chapter 5.
18. Figure 9.18 MTM‐5G map: packaging forms for for 5G mobility products.
19. Figure 9.19 Pillar‐land, pillar‐pad suitful for C2C, or C2W; left figure from [41], right figure from [42].
20. Figure 9.20 Pillar to pad for W2W, right from [43].
21. Figure 9.21 Qualcomm’s 3D front to back (F2B) SoC stacking without TSVs.
22. Figure 9.22 Illustrations of Cu to Cu pad bonding; front to back (F2B, left) and front to front (F2F, right).
23. Figure 9.23 Escape routing of 50 µm pitch bump and 4/4 µm line/space.[47]
24. Figure 9.24(a) Side views of Ga Tech glass, where ZEONIF is laminated on both sides of 30 µm thick glass.
25. Figure 9.24(b) Atotech side views of glass interposer.
26. Figure 9.25 Configuration (a, top), and Insertion loss from the vias (b, bottom).[35]
27. Figure 9.26 Advanced PKG solutions.[38]
28. Figure 9.27 A new business opportunity between MM and MTM,[40] and a third party that specializes in WLP and LPP is born.
29. Figure 9.28 FinFET where N=3 (Figure 9.29) and future transistor produced by carbon nanotube, N=4.
30. Figure 9.29 FinFET manufactured from regular and SOI silicon wafers. More etching time is required in regular silicon to form fin structures.
31. Figure 9.30 Mobile: LPDDR5 or wide I/O 2, and enterprise: high bandwidth memory (HBM, SK hynix) and hybrid memory cube (HMC, Micron, and Samsung).
32. Figure 9.31 AP with wide I/O Gen 2. The AP SoC at the bottom would need to be a massive multi‐core in order to support the wide I/O architecture.
33. Figure 9.32 Four‐plus‐one HMC has four‐RAM memory with one control logic.
34. Figure 9.33 A side‐view of HMC‐2, which relies on Serdes optical links and logic‐DRAM connection using active TSVs.
35. Figure 9.34 HBM‐2, GPU, and its supporting memory in HBM‐2 configuration. HBM‐2’s logic connection to GPU are done through 2.5D Si interposer (left) and 2.1D solution (Figures 9.4 and 9.5).
36. Figure 9.35 NFC, a combo of NFC controller and security IC.
37. Figure 9.36 Image sensor packaging: CLCC (left) and a module using TSVs (right).
38. Figure 9.37 IoT technology choices: WiFi, BT, Zigbee, reduced 3G or LTE, and 6 LoWPAN.
39. Figure 9.38 Comparison of Wifi, Bluetooth, sub‐1GHz, and Zigbee as networks for IoT.
40. Figure 9.39 Bluetooth and Zigbee appear two very different IoT technologies.
Appendix A
1. Figure A.1 Weibull plot illustrating dual mode break down of SiO₂p‐Si capacitor.
2. Figure A.2 The slope of the plot corresponds to E_a, see Black’s and Arrhenius’ equations (Equation (8.11) and Equation (8.15), respectively, in Chapter 8).[12]
3. Figure A.3 Electromigration data at 295°C, 2.5MA/cm² for Cu and Al(Cu) 0.3 µm wide single‐damascene M1 lines on tungsten‐studs.[13]
4. Figure A.4 Silicon dissolves in Al, forming a void filled by Al, becoming spikes under the interface areas of the grain boundaries, see also Figure 2.21 in Chapter 2.
5. Figure A.5 Three stages of strain versus time under constant loading (thermal).[23][24]
6. Figure A.6 Die edge crack from the low fillet height;[27] a picture of die edge crack can be found in [28].
7. Figure A.7 Plastic cracking, the so called popcorning, in a PLCC, due to thermal stress‐strain effect and the moisture absorbed.[26][30]
8. Figure A.8 After polishing the AuAl IMC micrographs can be obtained using IRM.
9. Figure A.9 B, A, and S, along with characteristic x‐rays created from bombardment of primary electron beams.
10. Figure A.10 AES (auger (OJ) electron spectroscopy), in which KLL electrons are involved.
Appendix B
1. Figure B.1 One‐way ANOVA.
Appendix C
1. Figure C.1 Single replicated (unreplicated) design, 16 observations in 4 factors.
2. Figure C.2a Minitab full model result for data in Figure C.1.
3. Figure C.2b A full model is possible even without the F and P statistics.
4. Figure C.3 Normal plot of the effects; factor B is not significant.
5. Figure C.4 Adding a nuisance factor to Example 6.2 of Chapter 6[3] by D. C. Montgomery; minus 20 from data 9 to 16 (see Figure C.1).
6. Figure C.5 Minitab result nuisance blocked.
7. Figure C.6 Treating the problem without blocking the nuisance factor.
8. Figure C.7a Panel‐Defect‐Data.MTW; residual is found after a model is obtained (see the following discussion).
9. Figure C.7b No d.f. left for error, and R‐sq = 100%.
10. Figure C.7c Main effects A and C are the dominant main effects.
11. Figure C.7d Design based only on main effects A and C (top portion), and a model is obtained (bottom).
12. Figure C.7e Normal probability of residues obtained using the model shown in Figure C.7d.
13. Figure C.7f Residuals versus Clamp_t.
14. Figure C.8 Replicated data; 16 (=2*2³) observations for three factors; not blocked.
15. Figure C.9a Minitab results for a replicated run; d.f. for error is 8.
16. Figure C.9b Treating a replicated data in blocks; the d.f. for error is 7.
17. Figure C.10 Repeated data from different wafers in the same spin.
18. Figure C.11 Ln(Stdev) of a repeated data set Oxide‐Thick‐Stdev.MTW, where the ratio effect was obtained.
19. Figure C.12 Center points (#17, 18, 19, and 20) are added to data in Figure C.1.
20. Figure C.13 Minitab result for Figure C.12; the d.f. for error = 3.
21. Figure C.14 D = ABC, or I = ABCD, or A = BCD, using Filtration‐Half.MTW.
22. Figure C.15 Model for the case shown in Figure C.14.
23. Figure C.16 Normal plot for the standardized effects.
24. Figure C.17 Effects corresponding to I = – ABCD, using Filtration‐Half‐Alt.MTW.
25. Figure C.18 2⁵⁻² FF design, the DGs are D = AB, E = AC.
26. Figure C.19 Example 8.4, Injection Molding, a quarter FF design, 2⁶⁻².
27. Figure C.20 Keep only factors A, B, and AB; R‐sq is 96.26%.
28. Figure C.21 Residual plot.
29. Figure C.22 Residual plot against factor C, the hold time.

3D IC and RF SiPs

Advanced Stacking and Planar Solutions for 5G Mobility